Friday 3 October 2014

Maxed Out: More on Using Transistors to Build Logic Functions

Maxed Out: More on Using Transistors to Build Logic Functions
Wednesday, June 04, 2008 | Clive "Max" Maxfield

In Part 7 of this series we discussed how to construct a NOT gate using (a) a single NMOS transistor (with a resistor), (b) a single PMOS transistor (with a resistor), and (c) as a CMOS implementation using a PMOS transistor and an NMOS transistor connected together in a complementary manner (Figure 1).

Figure 1. Three different implementations of an inverter (NOT gate).


In a moment we're going to look at CMOS implementations of other gates (BUF, NAND, and AND) gates, but while we do, I'd like you to ponder the following question: "Why do we predominantly use CMOS implementations as opposed to, say, NMOS implementations?" I mean, as we see in Figure 1, the CMOS gate requires two transistors, while the NMOS equivalent required only a single transistor and a resistor.
I'll be answering this question next time, so stay tuned and watch this space. But I digress.
CMOS implementation of a BUF Gate
Now, most folks instinctively think that it would be easier (and would require fewer transistors) to implement a non-inverting function like a BUF gate. As fate would have it, however, it' s usually easier to create inverting functions as opposed to their non-inverting counterparts. For example, in order to create a non-inverting BUF gate, we actually have to use two NOT gates as illustrated in Figure 2.



Figure 2. CMOS implementation of a BUF gate.


Don't panic, this isn't as complicated as it looks. Assume that we take a piece of wire and attach one end to input 'a.' We are holding the other end of the wire in our hands, and we can connect this other end to logic 0 or logic 1 (in reality, of course, input 'a' would be driven by the output from another logic gate).
If we connect input 'a' to logic 0, this will turn transistor T1 ON ("close the switch") and transistor T2 OFF ("open the switch"); this means that wire 'w' will be connected to logic 1 via transistor T1. Now, if wire 'w' is a logic 1, this will turn transistor T3 OFF and transistor T4 ON; this means that output 'y' will be connected to logic 0 via transistor T4.
By comparison, if we connect input 'a' to logic 1, this will turn transistor T1 OFF ("open the switch") and transistor T2 ON ("close the switch"); this means that wire 'w' will be connected to logic 0 via transistor T2. Now, if wire 'w' is a logic 0, this will turn transistor T3 ON and transistor T4 OFF; this means that output 'y' will be connected to logic 1 via transistor T3.
If you work this through, you'll see that we have indeed implemented a non-inverting BUF gate.
CMOS implementation of a NAND Gate
In the same way that it's easier to make an inverting NOT than it is to construct a non-inverting BUF, it's also easier to create an inverting NAND than it is to create a non-inverting AND. Let's see how this works. Consider the circuit shown in Figure 3.




Figure 3. CMOS implementation of a NAND gate.


Let's consider the "odd man out" case first. If inputs 'a' and 'b' are both logic 1, then transistors T1 and T2 will both be turned OFF, transistors T3 and T4 will both be turned ON, and output 'y' will be connected to logic 0 via transistors T3 and T4.
For any other combination of inputs, transistor T1 and/or T2 will be turned ON, transistor T3 and/or T4 will be turned OFF, and output 'y' will be connected to logic 1 via transistor T1 and/or T2.
CMOS implementation of an AND Gate
So, we have an inverting NAND gate but we really want a non-inverting AND. The way we achieve this is to invert the output of our NAND with a NOT as illustrated in Figure 4.

Figure 4. CMOS implementation of an AND gate.
As we see, the NAND requires four transistors (T1, T2, T3, and T4) and the NOT requires two transistors (T5 and T6), so the combination forming the AND requires six transistors.
Until Next Time
OK, in addition to the question I posed at the beginning of this column, here's another one for you. Can you see how to create a CMOS implementation of NOR and OR gates? Again, we discussed these concepts in previous columns. Until next time, have a good one!

Acknowledgements
This article was abstracted from Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) with the kind permission of the publisher.
About the author


Clive "Max" Maxfield is president of TechBites Interactive, a marketing consultancy firm specializing in high technology. Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics)The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows)How Computers Do Math featuring the pedagogical and phantasmagorical virtual DIY Calculator.

In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way. Max can be contacted at

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